PCIe Timing Interface Board

Document #:

LIGO-D2000329-v1

Document type:

D - Drawings

Abstract:

Schematics and PCB of the PCIe timing interface.

Files in Document:

• D2000329.pdf (4.6 MB)
• board-preview.pdf (294.5 kB)

Other Files:

• ChassisTimingInterface (8-12-2020).zip (11.7 MB)
• ChassisTimingInterface (8-28-2020).zip (12.9 MB)

ICS/JIRA Record:

• ICS_LINK

Topics:

• Data Acquisition System

Authors:

• Marc Pirello

Notes and Changes:

Remove R19 1k resistor, might improve XADC
Remove R127 power supply divider mistake
Replaced U43 and U40 wrong linear regulators
U2 part should be ADG706 but was stuffed with ADG707
Capacitor C148 should be 1nF and C22 should be 0.1uF both COG's..
R185 should be a 20 ohm resistor connected to BGND not U48. Remove R185 and rotate to BGND.
R46,R47,R140,R137 should be 100 ohm
R45 shoudl be 10k
Fix the kelvin connections for the PCIE sense resistors, R143.