| Rule Violations |
Count |
| Clearance Constraint (Gap=10mil) (HasFootprint('SOTFL50P160X60-6N')),(All) |
0 |
| Clearance Constraint (Gap=10mil) (InNetClass('Clearance8mils')),(InNetClass('Clearance8mils')) |
0 |
| Clearance Constraint (Gap=10mil) (All),(All) |
0 |
| Short-Circuit Constraint (Allowed=No) (All),(All) |
0 |
| Un-Routed Net Constraint ( (All) ) |
0 |
| Modified Polygon (Allow modified: No), (Allow shelved: No) |
0 |
| Width Constraint (Min=8mil) (Max=100mil) (Preferred=10mil) (All) |
0 |
| Routing Topology Rule(Topology=Shortest) (All) |
0 |
| Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) |
0 |
| Minimum Annular Ring (Minimum=10mil) (All) |
0 |
| Hole Size Constraint (Min=8mil) (Max=200mil) (All) |
0 |
| Hole To Hole Clearance (Gap=10mil) (All),(All) |
0 |
| Minimum Solder Mask Sliver (Gap=0mil) (All),(All) |
0 |
| Silk To Solder Mask (Clearance=2mil) (IsPad),(All) |
0 |
| Silk to Silk (Clearance=10mil) (All),(All) |
0 |
| Net Antennae (Tolerance=0mil) (All) |
0 |
| Room BIT5 (Bounding Region = (4000mil, 1825mil, 4650mil, 2200mil) (InComponentClass('BIT5')) |
0 |
| Room BIT2 (Bounding Region = (4000mil, 2950mil, 4650mil, 3325mil) (InComponentClass('BIT2')) |
0 |
| Room BIT0 (Bounding Region = (4000mil, 3700mil, 4650mil, 4075mil) (InComponentClass('BIT0')) |
0 |
| Room BIT1 (Bounding Region = (4000mil, 3325mil, 4650mil, 3700mil) (InComponentClass('BIT1')) |
0 |
| Room BIT3 (Bounding Region = (4000mil, 2575mil, 4650mil, 2950mil) (InComponentClass('BIT3')) |
0 |
| Room BIT6 (Bounding Region = (4000mil, 1450mil, 4650mil, 1825mil) (InComponentClass('BIT6')) |
0 |
| Room BIT7 (Bounding Region = (4000mil, 1075mil, 4650mil, 1450mil) (InComponentClass('BIT7')) |
0 |
| Room BIT4 (Bounding Region = (4000mil, 2200mil, 4650mil, 2575mil) (InComponentClass('BIT4')) |
0 |
| Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) |
0 |
| Total |
0 |
