Altium

Design Rule Verification Report

Date:		4/1/2021
Time:		2:22:21 PM
Elapsed Time:		00:00:01
Filename:		C:\Users\Daniel\Documents\Protel\marc.pirello\Solutions\ISC - PCIe Duotone\New Backplane\TestAdapter\TestAdapter.PcbDoc

Warnings:		0
Rule Violations:		0

Summary

Warnings	Count
Total	0

Rule Violations	Count
Clearance Constraint (Gap=10mil) (All),(All)	0
Short-Circuit Constraint (Allowed=No) (All),(All)	0
Un-Routed Net Constraint ( (All) )	0
Width Constraint (Min=10mil) (Max=100mil) (Preferred=10mil) (All)	0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)	0
Hole Size Constraint (Min=10mil) (Max=200mil) (All)	0
Hole To Hole Clearance (Gap=10mil) (All),(All)	0
Minimum Solder Mask Sliver (Gap=5mil) (All),(All)	0
Silk To Solder Mask (Clearance=0mil) (IsPad),(All)	0
Silk to Silk (Clearance=6mil) (All),(All)	0
Net Antennae (Tolerance=0mil) (All)	0
Component Clearance Constraint ( Horizontal Gap = 10mil, Vertical Gap = 10mil ) (All),(All)	0
Total	0