Design Rule Verification Report

Date:		7/20/2020
Time:		12:55:59 PM
Elapsed Time:		00:00:02
Filename:		C:\Users\Daniel\Documents\Protel\marc.pirello\Solutions\ISC - PCIe Duotone\PCIe_DaughterTemplate\PCIe_DaughterHalfLength.PcbDoc

Warnings:		0
Rule Violations:		0

Summary

Warnings	Count
Total	0

Rule Violations	Count
Clearance Constraint (Gap=5mil) (All),(All)	0
Short-Circuit Constraint (Allowed=No) (All),(All)	0
Un-Routed Net Constraint ( (All) )	0
Width Constraint (Min=5mil) (Max=196.85mil) (Preferred=10mil) (All)	0
Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)	0
Total	0