Altium

Design Rule Verification Report

Date: 11/10/2020
Time: 1:50:42 PM
Elapsed Time: 00:00:01
Filename: C:\Users\Daniel\Documents\Protel\marc.pirello\Solutions\ISC - PCIe Duotone\PCIe_Master\Master.PcbDoc
Warnings: 0
Rule Violations: 0

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=6mil) (All),(All) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Width Constraint (Min=6mil) (Max=50mil) (Preferred=8.5mil) (All) 0
Differential Pairs Uncoupled Length using the Gap Constraints (Min=6mil) (Max=10mil) (Prefered=10mil) and Width Constraints (Min=7mil) (Max=8.5mil) (Prefered=8.5mil) (All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=10mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Minimum Annular Ring (Minimum=5mil) (All) 0
Hole Size Constraint (Min=10mil) (Max=150mil) (All) 0
Pads and Vias to follow the Drill pairs settings 0
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Minimum Solder Mask Sliver (Gap=1mil) (All),(All) 0
Minimum Solder Mask Sliver (Gap=1mil) (HasFootprint('MSOP8')),(HasFootprint('MSOP8')) 0
Minimum Solder Mask Sliver (Gap=0mil) (HasFootprint('LED-0603')),(All) 0
Silk To Solder Mask (Clearance=0mil) (IsPad),(All) 0
Silk to Silk (Clearance=5mil) (All),(All) 0
Net Antennae (Tolerance=0mil) (All) 0
Component Clearance Constraint ( Horizontal Gap = -10000mil, Vertical Gap = 10mil ) (InComponent('J1CAGE')),(InComponent('J1C')) 0
Component Clearance Constraint ( Horizontal Gap = -10000mil, Vertical Gap = 10mil ) (InComponent('J1CAGE')),(InComponent('J1A')) 0
Component Clearance Constraint ( Horizontal Gap = -10000mil, Vertical Gap = 10mil ) (InComponent('J1CAGE')),(InComponent('J1B')) 0
Height Constraint (Min=0mil) (Max=1200mil) (Prefered=500mil) (All) 0
Total 0