Static Timing Analysis

Project : CPSSynch
Build Time : 01/06/15 13:14:39
Device : CY8C3866AXI-040
Temperature : -40C - 85/125C
Vdda : 5.00
Vddd : 5.00
Vio0 : 5.00
Vio1 : 5.00
Vio2 : 5.00
Vio3 : 5.00
Voltage : 5.0
Vusb : 5.00
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
Clock_2(routed) Clock_2(routed) 1.543 MHz 1.543 MHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 35.500 MHz 35.500 MHz N/A
CyMASTER_CLK CyMASTER_CLK 35.500 MHz 35.500 MHz N/A
Clock_2 CyMASTER_CLK 1.543 MHz 1.543 MHz 116.891 MHz
CyBUS_CLK CyMASTER_CLK 35.500 MHz 35.500 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 647.887ns(1.54348 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
Net_19/q Net_19/main_1 116.891 MHz 8.555 639.332
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(0,4) 1 Net_19 Net_19/clock_0 Net_19/q 1.250
macrocell1 U(0,4) 1 Net_19 Net_19/q Net_19/main_1 3.795
macrocell1 U(0,4) 1 Net_19 SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:count_4\/q Net_19/main_3 132.363 MHz 7.555 640.332
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(0,4) 1 \FreqDiv_1:count_4\ \FreqDiv_1:count_4\/clock_0 \FreqDiv_1:count_4\/q 1.250
Route 1 \FreqDiv_1:count_4\ \FreqDiv_1:count_4\/q Net_19/main_3 2.795
macrocell1 U(0,4) 1 Net_19 SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:count_4\/q \FreqDiv_1:count_2\/main_2 132.363 MHz 7.555 640.332
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(0,4) 1 \FreqDiv_1:count_4\ \FreqDiv_1:count_4\/clock_0 \FreqDiv_1:count_4\/q 1.250
Route 1 \FreqDiv_1:count_4\ \FreqDiv_1:count_4\/q \FreqDiv_1:count_2\/main_2 2.795
macrocell4 U(0,4) 1 \FreqDiv_1:count_2\ SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:count_4\/q \FreqDiv_1:count_3\/main_2 132.363 MHz 7.555 640.332
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(0,4) 1 \FreqDiv_1:count_4\ \FreqDiv_1:count_4\/clock_0 \FreqDiv_1:count_4\/q 1.250
Route 1 \FreqDiv_1:count_4\ \FreqDiv_1:count_4\/q \FreqDiv_1:count_3\/main_2 2.795
macrocell5 U(0,4) 1 \FreqDiv_1:count_3\ SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:count_4\/q \FreqDiv_1:count_4\/main_2 132.485 MHz 7.548 640.339
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(0,4) 1 \FreqDiv_1:count_4\ \FreqDiv_1:count_4\/clock_0 \FreqDiv_1:count_4\/q 1.250
macrocell6 U(0,4) 1 \FreqDiv_1:count_4\ \FreqDiv_1:count_4\/q \FreqDiv_1:count_4\/main_2 2.788
macrocell6 U(0,4) 1 \FreqDiv_1:count_4\ SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:count_4\/q \FreqDiv_1:count_5\/main_2 132.485 MHz 7.548 640.339
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(0,4) 1 \FreqDiv_1:count_4\ \FreqDiv_1:count_4\/clock_0 \FreqDiv_1:count_4\/q 1.250
Route 1 \FreqDiv_1:count_4\ \FreqDiv_1:count_4\/q \FreqDiv_1:count_5\/main_2 2.788
macrocell7 U(0,4) 1 \FreqDiv_1:count_5\ SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:count_5\/q Net_19/main_2 132.503 MHz 7.547 640.340
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(0,4) 1 \FreqDiv_1:count_5\ \FreqDiv_1:count_5\/clock_0 \FreqDiv_1:count_5\/q 1.250
Route 1 \FreqDiv_1:count_5\ \FreqDiv_1:count_5\/q Net_19/main_2 2.787
macrocell1 U(0,4) 1 Net_19 SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:count_5\/q \FreqDiv_1:count_2\/main_1 132.503 MHz 7.547 640.340
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(0,4) 1 \FreqDiv_1:count_5\ \FreqDiv_1:count_5\/clock_0 \FreqDiv_1:count_5\/q 1.250
Route 1 \FreqDiv_1:count_5\ \FreqDiv_1:count_5\/q \FreqDiv_1:count_2\/main_1 2.787
macrocell4 U(0,4) 1 \FreqDiv_1:count_2\ SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:count_5\/q \FreqDiv_1:count_3\/main_1 132.503 MHz 7.547 640.340
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(0,4) 1 \FreqDiv_1:count_5\ \FreqDiv_1:count_5\/clock_0 \FreqDiv_1:count_5\/q 1.250
Route 1 \FreqDiv_1:count_5\ \FreqDiv_1:count_5\/q \FreqDiv_1:count_3\/main_1 2.787
macrocell5 U(0,4) 1 \FreqDiv_1:count_3\ SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:not_last_reset\/q Net_19/main_0 132.521 MHz 7.546 640.341
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(0,4) 1 \FreqDiv_1:not_last_reset\ \FreqDiv_1:not_last_reset\/clock_0 \FreqDiv_1:not_last_reset\/q 1.250
Route 1 \FreqDiv_1:not_last_reset\ \FreqDiv_1:not_last_reset\/q Net_19/main_0 2.786
macrocell1 U(0,4) 1 Net_19 SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\FreqDiv_1:count_3\/q \FreqDiv_1:count_4\/main_3 3.846
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(0,4) 1 \FreqDiv_1:count_3\ \FreqDiv_1:count_3\/clock_0 \FreqDiv_1:count_3\/q 1.250
Route 1 \FreqDiv_1:count_3\ \FreqDiv_1:count_3\/q \FreqDiv_1:count_4\/main_3 2.596
macrocell6 U(0,4) 1 \FreqDiv_1:count_4\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_3\/q \FreqDiv_1:count_5\/main_3 3.846
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(0,4) 1 \FreqDiv_1:count_3\ \FreqDiv_1:count_3\/clock_0 \FreqDiv_1:count_3\/q 1.250
Route 1 \FreqDiv_1:count_3\ \FreqDiv_1:count_3\/q \FreqDiv_1:count_5\/main_3 2.596
macrocell7 U(0,4) 1 \FreqDiv_1:count_5\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_3\/q Net_19/main_4 3.848
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(0,4) 1 \FreqDiv_1:count_3\ \FreqDiv_1:count_3\/clock_0 \FreqDiv_1:count_3\/q 1.250
Route 1 \FreqDiv_1:count_3\ \FreqDiv_1:count_3\/q Net_19/main_4 2.598
macrocell1 U(0,4) 1 Net_19 HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_3\/q \FreqDiv_1:count_2\/main_3 3.848
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(0,4) 1 \FreqDiv_1:count_3\ \FreqDiv_1:count_3\/clock_0 \FreqDiv_1:count_3\/q 1.250
Route 1 \FreqDiv_1:count_3\ \FreqDiv_1:count_3\/q \FreqDiv_1:count_2\/main_3 2.598
macrocell4 U(0,4) 1 \FreqDiv_1:count_2\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_3\/q \FreqDiv_1:count_3\/main_3 3.848
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(0,4) 1 \FreqDiv_1:count_3\ \FreqDiv_1:count_3\/clock_0 \FreqDiv_1:count_3\/q 1.250
macrocell5 U(0,4) 1 \FreqDiv_1:count_3\ \FreqDiv_1:count_3\/q \FreqDiv_1:count_3\/main_3 2.598
macrocell5 U(0,4) 1 \FreqDiv_1:count_3\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_0\/q Net_19/main_7 3.852
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(0,4) 1 \FreqDiv_1:count_0\ \FreqDiv_1:count_0\/clock_0 \FreqDiv_1:count_0\/q 1.250
Route 1 \FreqDiv_1:count_0\ \FreqDiv_1:count_0\/q Net_19/main_7 2.602
macrocell1 U(0,4) 1 Net_19 HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_0\/q \FreqDiv_1:count_2\/main_6 3.852
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(0,4) 1 \FreqDiv_1:count_0\ \FreqDiv_1:count_0\/clock_0 \FreqDiv_1:count_0\/q 1.250
Route 1 \FreqDiv_1:count_0\ \FreqDiv_1:count_0\/q \FreqDiv_1:count_2\/main_6 2.602
macrocell4 U(0,4) 1 \FreqDiv_1:count_2\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_0\/q \FreqDiv_1:count_3\/main_6 3.852
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(0,4) 1 \FreqDiv_1:count_0\ \FreqDiv_1:count_0\/clock_0 \FreqDiv_1:count_0\/q 1.250
Route 1 \FreqDiv_1:count_0\ \FreqDiv_1:count_0\/q \FreqDiv_1:count_3\/main_6 2.602
macrocell5 U(0,4) 1 \FreqDiv_1:count_3\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_0\/q \FreqDiv_1:count_1\/main_1 3.854
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(0,4) 1 \FreqDiv_1:count_0\ \FreqDiv_1:count_0\/clock_0 \FreqDiv_1:count_0\/q 1.250
Route 1 \FreqDiv_1:count_0\ \FreqDiv_1:count_0\/q \FreqDiv_1:count_1\/main_1 2.604
macrocell3 U(0,4) 1 \FreqDiv_1:count_1\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_0\/q \FreqDiv_1:count_4\/main_6 3.854
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(0,4) 1 \FreqDiv_1:count_0\ \FreqDiv_1:count_0\/clock_0 \FreqDiv_1:count_0\/q 1.250
Route 1 \FreqDiv_1:count_0\ \FreqDiv_1:count_0\/q \FreqDiv_1:count_4\/main_6 2.604
macrocell6 U(0,4) 1 \FreqDiv_1:count_4\ HOLD 0.000
Clock Skew 0.000
+ Input To Output Section
Source Destination Delay (ns)
Alive(0)_PAD BoardLEDOut(0)_PAD 31.365
Type Location Fanout Instance/Net Source Dest Delay (ns)
CPSSynch 1 Alive(0)_PAD Alive(0)_PAD Alive(0)_PAD 0.000
Route 1 Alive(0)_PAD Alive(0)_PAD Alive(0)/pad_in 0.000
iocell1 P4[2] 1 Alive(0) Alive(0)/pad_in Alive(0)/fb 7.260
Route 1 Net_129 Alive(0)/fb BoardLEDOut(0)/pin_input 8.365
iocell2 P6[3] 1 BoardLEDOut(0) BoardLEDOut(0)/pin_input BoardLEDOut(0)/pad_out 15.740
Route 1 BoardLEDOut(0)_PAD BoardLEDOut(0)/pad_out BoardLEDOut(0)_PAD 0.000
Alive(0)_PAD LEDOut(0)_PAD 27.271
Type Location Fanout Instance/Net Source Dest Delay (ns)
CPSSynch 1 Alive(0)_PAD Alive(0)_PAD Alive(0)_PAD 0.000
Route 1 Alive(0)_PAD Alive(0)_PAD Alive(0)/pad_in 0.000
iocell1 P4[2] 1 Alive(0) Alive(0)/pad_in Alive(0)/fb 7.260
Route 1 Net_129 Alive(0)/fb LEDOut(0)/pin_input 4.236
iocell3 P0[0] 1 LEDOut(0) LEDOut(0)/pin_input LEDOut(0)/pad_out 15.775
Route 1 LEDOut(0)_PAD LEDOut(0)/pad_out LEDOut(0)_PAD 0.000
+ Clock To Output Section
+ Clock_2
Source Destination Delay (ns)
Net_19/q Pin_7(0)_PAD 28.343
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(0,4) 1 Net_19 Net_19/clock_0 Net_19/q 1.250
Route 1 Net_19 Net_19/q Pin_7(0)/pin_input 11.498
iocell16 P5[5] 1 Pin_7(0) Pin_7(0)/pin_input Pin_7(0)/pad_out 15.595
Route 1 Pin_7(0)_PAD Pin_7(0)/pad_out Pin_7(0)_PAD 0.000
Clock Clock path delay 0.000
Net_19/q Pin_1(0)_PAD 28.325
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(0,4) 1 Net_19 Net_19/clock_0 Net_19/q 1.250
Route 1 Net_19 Net_19/q Pin_1(0)/pin_input 11.498
iocell4 P5[7] 1 Pin_1(0) Pin_1(0)/pin_input Pin_1(0)/pad_out 15.577
Route 1 Pin_1(0)_PAD Pin_1(0)/pad_out Pin_1(0)_PAD 0.000
Clock Clock path delay 0.000
Net_19/q Pin_6(0)_PAD 27.163
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(0,4) 1 Net_19 Net_19/clock_0 Net_19/q 1.250
Route 1 Net_19 Net_19/q Pin_6(0)/pin_input 10.290
iocell15 P1[6] 1 Pin_6(0) Pin_6(0)/pin_input Pin_6(0)/pad_out 15.623
Route 1 Pin_6(0)_PAD Pin_6(0)/pad_out Pin_6(0)_PAD 0.000
Clock Clock path delay 0.000
Net_19/q Pin_5(0)_PAD 27.104
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(0,4) 1 Net_19 Net_19/clock_0 Net_19/q 1.250
Route 1 Net_19 Net_19/q Pin_5(0)/pin_input 10.290
iocell14 P1[5] 1 Pin_5(0) Pin_5(0)/pin_input Pin_5(0)/pad_out 15.564
Route 1 Pin_5(0)_PAD Pin_5(0)/pad_out Pin_5(0)_PAD 0.000
Clock Clock path delay 0.000
Net_19/q Pin_2(0)_PAD 24.567
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(0,4) 1 Net_19 Net_19/clock_0 Net_19/q 1.250
Route 1 Net_19 Net_19/q Pin_2(0)/pin_input 7.579
iocell11 P2[2] 1 Pin_2(0) Pin_2(0)/pin_input Pin_2(0)/pad_out 15.738
Route 1 Pin_2(0)_PAD Pin_2(0)/pad_out Pin_2(0)_PAD 0.000
Clock Clock path delay 0.000
Net_19/q Pin_4(0)_PAD 24.497
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(0,4) 1 Net_19 Net_19/clock_0 Net_19/q 1.250
Route 1 Net_19 Net_19/q Pin_4(0)/pin_input 7.553
iocell13 P2[6] 1 Pin_4(0) Pin_4(0)/pin_input Pin_4(0)/pad_out 15.694
Route 1 Pin_4(0)_PAD Pin_4(0)/pad_out Pin_4(0)_PAD 0.000
Clock Clock path delay 0.000
Net_19/q Pin_3(0)_PAD 23.638
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(0,4) 1 Net_19 Net_19/clock_0 Net_19/q 1.250
Route 1 Net_19 Net_19/q Pin_3(0)/pin_input 7.553
iocell12 P2[5] 1 Pin_3(0) Pin_3(0)/pin_input Pin_3(0)/pad_out 14.835
Route 1 Pin_3(0)_PAD Pin_3(0)/pad_out Pin_3(0)_PAD 0.000
Clock Clock path delay 0.000
+ Clock_2(routed)
Source Destination Delay (ns)
ClockBlock/dclk_0 Pin_8(0)_PAD 30.495
Type Location Fanout Instance/Net Source Dest Delay (ns)
clockblockcell F(Clock,0) 1 ClockBlock Input Delay ClockBlock/dclk_0 0.000
Route 1 Net_107_local ClockBlock/dclk_0 Pin_8(0)/pin_input 14.618
iocell17 P5[6] 1 Pin_8(0) Pin_8(0)/pin_input Pin_8(0)/pad_out 15.877
Route 1 Pin_8(0)_PAD Pin_8(0)/pad_out Pin_8(0)_PAD 0.000
Clock Clock path delay 0.000
ClockBlock/dclk_0 Pin_8(0)_PAD 30.495
Type Location Fanout Instance/Net Source Dest Delay (ns)
clockblockcell F(Clock,0) 1 ClockBlock Input Delay ClockBlock/dclk_0 0.000
Route 1 Net_107_local ClockBlock/dclk_0 Pin_8(0)/pin_input 14.618
iocell17 P5[6] 1 Pin_8(0) Pin_8(0)/pin_input Pin_8(0)/pad_out 15.877
Route 1 Pin_8(0)_PAD Pin_8(0)/pad_out Pin_8(0)_PAD 0.000
Clock Clock path delay 0.000
ClockBlock/dclk_0 Pin_14(0)_PAD 29.974
Type Location Fanout Instance/Net Source Dest Delay (ns)
clockblockcell F(Clock,0) 1 ClockBlock Input Delay ClockBlock/dclk_0 0.000
Route 1 Net_107_local ClockBlock/dclk_0 Pin_14(0)/pin_input 14.618
iocell9 P5[4] 1 Pin_14(0) Pin_14(0)/pin_input Pin_14(0)/pad_out 15.356
Route 1 Pin_14(0)_PAD Pin_14(0)/pad_out Pin_14(0)_PAD 0.000
Clock Clock path delay 0.000
ClockBlock/dclk_0 Pin_14(0)_PAD 29.974
Type Location Fanout Instance/Net Source Dest Delay (ns)
clockblockcell F(Clock,0) 1 ClockBlock Input Delay ClockBlock/dclk_0 0.000
Route 1 Net_107_local ClockBlock/dclk_0 Pin_14(0)/pin_input 14.618
iocell9 P5[4] 1 Pin_14(0) Pin_14(0)/pin_input Pin_14(0)/pad_out 15.356
Route 1 Pin_14(0)_PAD Pin_14(0)/pad_out Pin_14(0)_PAD 0.000
Clock Clock path delay 0.000
ClockBlock/dclk_0 Pin_13(0)_PAD 29.567
Type Location Fanout Instance/Net Source Dest Delay (ns)
clockblockcell F(Clock,0) 1 ClockBlock Input Delay ClockBlock/dclk_0 0.000
Route 1 Net_107_local ClockBlock/dclk_0 Pin_13(0)/pin_input 13.403
iocell8 P1[7] 1 Pin_13(0) Pin_13(0)/pin_input Pin_13(0)/pad_out 16.164
Route 1 Pin_13(0)_PAD Pin_13(0)/pad_out Pin_13(0)_PAD 0.000
Clock Clock path delay 0.000
ClockBlock/dclk_0 Pin_13(0)_PAD 29.567
Type Location Fanout Instance/Net Source Dest Delay (ns)
clockblockcell F(Clock,0) 1 ClockBlock Input Delay ClockBlock/dclk_0 0.000
Route 1 Net_107_local ClockBlock/dclk_0 Pin_13(0)/pin_input 13.403
iocell8 P1[7] 1 Pin_13(0) Pin_13(0)/pin_input Pin_13(0)/pad_out 16.164
Route 1 Pin_13(0)_PAD Pin_13(0)/pad_out Pin_13(0)_PAD 0.000
Clock Clock path delay 0.000
ClockBlock/dclk_0 Pin_12(0)_PAD 28.564
Type Location Fanout Instance/Net Source Dest Delay (ns)
clockblockcell F(Clock,0) 1 ClockBlock Input Delay ClockBlock/dclk_0 0.000
Route 1 Net_107_local ClockBlock/dclk_0 Pin_12(0)/pin_input 13.415
iocell7 P1[2] 1 Pin_12(0) Pin_12(0)/pin_input Pin_12(0)/pad_out 15.149
Route 1 Pin_12(0)_PAD Pin_12(0)/pad_out Pin_12(0)_PAD 0.000
Clock Clock path delay 0.000
ClockBlock/dclk_0 Pin_12(0)_PAD 28.564
Type Location Fanout Instance/Net Source Dest Delay (ns)
clockblockcell F(Clock,0) 1 ClockBlock Input Delay ClockBlock/dclk_0 0.000
Route 1 Net_107_local ClockBlock/dclk_0 Pin_12(0)/pin_input 13.415
iocell7 P1[2] 1 Pin_12(0) Pin_12(0)/pin_input Pin_12(0)/pad_out 15.149
Route 1 Pin_12(0)_PAD Pin_12(0)/pad_out Pin_12(0)_PAD 0.000
Clock Clock path delay 0.000
ClockBlock/dclk_0 Pin_9(0)_PAD 26.288
Type Location Fanout Instance/Net Source Dest Delay (ns)
clockblockcell F(Clock,0) 1 ClockBlock Input Delay ClockBlock/dclk_0 0.000
Route 1 Net_107_local ClockBlock/dclk_0 Pin_9(0)/pin_input 10.620
iocell18 P2[3] 1 Pin_9(0) Pin_9(0)/pin_input Pin_9(0)/pad_out 15.668
Route 1 Pin_9(0)_PAD Pin_9(0)/pad_out Pin_9(0)_PAD 0.000
Clock Clock path delay 0.000
ClockBlock/dclk_0 Pin_9(0)_PAD 26.288
Type Location Fanout Instance/Net Source Dest Delay (ns)
clockblockcell F(Clock,0) 1 ClockBlock Input Delay ClockBlock/dclk_0 0.000
Route 1 Net_107_local ClockBlock/dclk_0 Pin_9(0)/pin_input 10.620
iocell18 P2[3] 1 Pin_9(0) Pin_9(0)/pin_input Pin_9(0)/pad_out 15.668
Route 1 Pin_9(0)_PAD Pin_9(0)/pad_out Pin_9(0)_PAD 0.000
Clock Clock path delay 0.000
ClockBlock/dclk_0 Pin_11(0)_PAD 26.202
Type Location Fanout Instance/Net Source Dest Delay (ns)
clockblockcell F(Clock,0) 1 ClockBlock Input Delay ClockBlock/dclk_0 0.000
Route 1 Net_107_local ClockBlock/dclk_0 Pin_11(0)/pin_input 10.543
iocell6 P2[7] 1 Pin_11(0) Pin_11(0)/pin_input Pin_11(0)/pad_out 15.659
Route 1 Pin_11(0)_PAD Pin_11(0)/pad_out Pin_11(0)_PAD 0.000
Clock Clock path delay 0.000
ClockBlock/dclk_0 Pin_11(0)_PAD 26.202
Type Location Fanout Instance/Net Source Dest Delay (ns)
clockblockcell F(Clock,0) 1 ClockBlock Input Delay ClockBlock/dclk_0 0.000
Route 1 Net_107_local ClockBlock/dclk_0 Pin_11(0)/pin_input 10.543
iocell6 P2[7] 1 Pin_11(0) Pin_11(0)/pin_input Pin_11(0)/pad_out 15.659
Route 1 Pin_11(0)_PAD Pin_11(0)/pad_out Pin_11(0)_PAD 0.000
Clock Clock path delay 0.000
ClockBlock/dclk_0 Pin_10(0)_PAD 26.102
Type Location Fanout Instance/Net Source Dest Delay (ns)
clockblockcell F(Clock,0) 1 ClockBlock Input Delay ClockBlock/dclk_0 0.000
Route 1 Net_107_local ClockBlock/dclk_0 Pin_10(0)/pin_input 10.543
iocell5 P2[4] 1 Pin_10(0) Pin_10(0)/pin_input Pin_10(0)/pad_out 15.559
Route 1 Pin_10(0)_PAD Pin_10(0)/pad_out Pin_10(0)_PAD 0.000
Clock Clock path delay 0.000
ClockBlock/dclk_0 Pin_10(0)_PAD 26.102
Type Location Fanout Instance/Net Source Dest Delay (ns)
clockblockcell F(Clock,0) 1 ClockBlock Input Delay ClockBlock/dclk_0 0.000
Route 1 Net_107_local ClockBlock/dclk_0 Pin_10(0)/pin_input 10.543
iocell5 P2[4] 1 Pin_10(0) Pin_10(0)/pin_input Pin_10(0)/pad_out 15.559
Route 1 Pin_10(0)_PAD Pin_10(0)/pad_out Pin_10(0)_PAD 0.000
Clock Clock path delay 0.000