Static Timing Analysis

Project : PulserTest
Build Time : 11/06/14 13:36:22
Device : CY8C3866AXI-040
Temperature : -40C - 85/125C
Vdda : 5.00
Vddd : 5.00
Vio0 : 5.00
Vio1 : 5.00
Vio2 : 5.00
Vio3 : 5.00
Voltage : 5.0
Vusb : 5.00
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_DelSig_1_Ext_CP_Clk ADC_DelSig_1_Ext_CP_Clk 24.000 MHz 24.000 MHz N/A
ADC_DelSig_1_Ext_CP_Clk(routed) ADC_DelSig_1_Ext_CP_Clk(routed) 24.000 MHz 24.000 MHz N/A
ADC_DelSig_1_theACLK(fixed-function) ADC_DelSig_1_theACLK(fixed-function) 631.579 kHz 631.579 kHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
ADC_DelSig_1_theACLK CyMASTER_CLK 631.579 kHz 631.579 kHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
\ADC_DelSig_1:DSM\/dec_clock \ADC_DelSig_1:DSM\/dec_clock UNKNOWN UNKNOWN N/A
+ Clock To Output Section
+ CyBUS_CLK
Source Destination Delay (ns)
UnderVFault(0)/fb Fault_Bit(0)_PAD 35.146
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell19 P2[7] 1 UnderVFault(0) UnderVFault(0)/in_clock UnderVFault(0)/fb 1.275
Route 1 Net_776 UnderVFault(0)/fb fault/main_1 8.098
macrocell4 U(3,1) 1 fault fault/main_1 fault/q 3.350
Route 1 fault fault/q Fault_Bit(0)/pin_input 6.170
iocell4 P12[1] 1 Fault_Bit(0) Fault_Bit(0)/pin_input Fault_Bit(0)/pad_out 16.253
Route 1 Fault_Bit(0)_PAD Fault_Bit(0)/pad_out Fault_Bit(0)_PAD 0.000
Clock Clock path delay 0.000
CoilRMon(0)/fb myRmon(0)_PAD 33.907
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[0] 1 CoilRMon(0) CoilRMon(0)/in_clock CoilRMon(0)/fb 1.801
Route 1 Net_777 CoilRMon(0)/fb coil/main_0 5.319
macrocell3 U(3,1) 1 coil coil/main_0 coil/q 3.350
Route 1 coil coil/q myRmon(0)/pin_input 7.339
iocell28 P0[5] 1 myRmon(0) myRmon(0)/pin_input myRmon(0)/pad_out 16.098
Route 1 myRmon(0)_PAD myRmon(0)/pad_out myRmon(0)_PAD 0.000
Clock Clock path delay 0.000
FastHigh(0)/fb myFast(0)_PAD 33.711
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P5[7] 1 FastHigh(0) FastHigh(0)/in_clock FastHigh(0)/fb 1.564
Route 1 Net_662 FastHigh(0)/fb Net_823/main_0 7.281
macrocell1 U(3,1) 1 Net_823 Net_823/main_0 Net_823/q 3.350
Route 1 Net_823 Net_823/q myFast(0)/pin_input 5.486
iocell27 P15[3] 1 myFast(0) myFast(0)/pin_input myFast(0)/pad_out 16.030
Route 1 myFast(0)_PAD myFast(0)/pad_out myFast(0)_PAD 0.000
Clock Clock path delay 0.000