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Design Rule Verification Report
Date
:
3/7/2007
Time
:
7:41:17 PM
Elapsed Time
:
00:00:00
Filename
:
C:\User\Daniel\Protel\Converter\SynchBuck\PowerMonitor.PcbDoc
Summary
Warnings
Count
Total
0
Rule Violations
Count
Clearance Constraint (Gap=8mil) (All),(All)
0
Width Constraint (Min=8mil) (Max=400mil) (Preferred=8mil) (All)
0
Hole Size Constraint (Min=1mil) (Max=125mil) (All)
0
Height Constraint (Min=0mil) (Max=2000mil) (Prefered=500mil) (All)
0
Broken-Net Constraint ( (All) )
0
Short-Circuit Constraint (Allowed=No) (All),(All)
0
Total
0