Altium

Design Rule Verification Report

Date:		6/18/2025
Time:		12:52:40 PM
Elapsed Time:		00:00:00
Filename:		C:\Users\daniel.sigg\Documents\Protel\PZTDriver\PZTDriverBoard.PcbDoc

Warnings:		0
Rule Violations:		0

Summary

Warnings	Count
Total	0

Rule Violations	Count
Clearance Constraint (Gap=8mil) (All),(All)	0
Clearance Constraint (Gap=35mil) ((InNet('N') OR InNet('P') OR InNet('PHV') OR InNet('NHV') OR InNet('HVFB') OR InNet('HVOUT'))),(All)	0
Clearance Constraint (Gap=8mil) ((HasFootprint('MSOP10'))),(All)	0
Short-Circuit Constraint (Allowed=No) (All),(All)	0
Un-Routed Net Constraint ( (All) )	0
Width Constraint (Min=8mil) (Max=100mil) (Preferred=12mil) (All)	0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)	0
Hole Size Constraint (Min=15mil) (Max=250mil) (All)	0
Hole To Hole Clearance (Gap=10mil) (All),(All)	0
Minimum Solder Mask Sliver (Gap=0mil) (All),(All)	0
Silk To Solder Mask (Clearance=0mil) (IsPad),(All)	0
Silk to Silk (Clearance=0mil) (All),(All)	0
Net Antennae (Tolerance=0mil) (All)	0
Height Constraint (Min=0mil) (Max=1200mil) (Prefered=500mil) (All)	0
Total	0